Manufacturers and designers of integrated circuit (IC) devices, such as memory controllers or processors, continue to increase the amount of signals that these devices can transmit and/or receive over a period of time (bandwidth). For example, processors having multiple cores have enabled, at least in part, increased processor bandwidth that may be used in communicating with IC memory devices.
Conventional memory devices will have difficulty increasing their bandwidths to meet the ever increasing demand. For example, dynamic random access memory (DRAM) arrays are scaling to provide more storage, but the speed of memory-cell access is remaining fairly constant due to physical constraints on the structures used to store and retrieve data. Memory bandwidth can be increased by accessing more data bits in parallel, but doing so in conventional memory architectures dramatically increases power use and area requirements. There is therefore a need for memory architectures, circuits, and methods that increase memory bandwidth without undue increases in power consumption, area, or circuit complexity.
Conventional memory devices, including DRAMs, include redundant columns of memory cells and related repair circuitry to compensate for defective memory resources (e.g., defective memory cells). The repair circuitry typically disables a column associated with defect memory resources and substitutes the disabled column with a redundant column provided for this purpose. Substituting a defective column takes time, however, and can therefore increase the time required to access the memory. There is therefore a need for improved methods and circuits for substituting defective memory resources.